How this instrument works
Inside an NE555, three equal internal resistors — the part's namesake — set two comparator thresholds at exactly one-third and two-thirds of the supply voltage. Wired as an astable multivibrator, the timing capacitor C charges toward the supply through R1 and R2 in series; the instant it crosses two-thirds Vcc, an internal transistor grounds the R2-C junction through the discharge pin, and C drains back down through R2 alone until it hits one-third Vcc, when charging resumes. That repeating climb and fall between the two thresholds is the oscillation, and R1, R2, and C are the only three things that set its pace.
Both timing halves come from the same RC charging law, V(t) = Vcc − (Vcc − V0)e^(−t/RC). Solving that equation for the time needed to travel from one-third to two-thirds of Vcc gives t = RC·ln2, which is where the 0.693 in t_high = 0.693(R1+R2)C and t_low = 0.693·R2·C comes from, since ln2 ≈ 0.6931. Because the capacitor charges through R1 and R2 together but discharges through R2 alone, t_high can never be shorter than t_low for any positive R1 — the duty cycle (R1+R2)/(R1+2R2) only creeps toward 50% as R1 shrinks toward zero, and never quite reaches or falls below it in this three-terminal RC topology.
The frequency formula's 1.44 is a rounded stand-in for 1/ln2, which is closer to 1.4427. That small rounding means 1/f and t_high + t_low don't quite agree — a difference under a quarter of one percent, invisible next to the ±5% resistors and ±10-20% capacitors that actually set real-world timing accuracy. A second, sharper limit: datasheets forbid R1 = 0. At that value the discharge transistor would briefly tie the supply straight to ground every cycle, a current spike through the discharge pin large enough to damage the chip, so R1 always needs a safe minimum, commonly a few hundred ohms or more.
- Enter R1, the resistor tying the supply rail to the discharge and threshold node, in ohms or kilohms.
- Enter R2, the resistor between the discharge pin and the capacitor node; it alone carries the discharge current, so keep it comfortably above zero.
- Enter the Timing capacitor value, the part labeled C, wired from that same node to ground.
- Read Oscillation frequency and Duty cycle, % for the steady output waveform on pin 3.
- Check Time high and Time low separately when you need the individual pulse widths, for example to confirm a following logic gate's setup time.
Worked example — a 686 Hz tone from 1 kΩ, 10 kΩ, and 0.1 µF
Set R1 to 1 kΩ (1000 Ω), R2 to 10 kΩ (10000 Ω), and the timing capacitor to 0.1 µF (1×10⁻⁷ F) — a common starting point for a simple audio tone or code-practice oscillator. Frequency: f = 1.44 ⁄ ((1000 + 20000) × 1×10⁻⁷) = 1.44 ⁄ 0.0021 = 685.714285714 Hz, comfortably inside the audio range. Duty cycle: (1000 + 10000) ⁄ (1000 + 20000) × 100 = 52.380952381%, just over half, exactly as the topology's asymmetric charge and discharge paths predict.
The individual pulse widths confirm the same asymmetry directly. Time high: t_high = 0.693 × (1000 + 10000) × 1×10⁻⁷ = 0.0007623 s, or 0.7623 ms. Time low: t_low = 0.693 × 10000 × 1×10⁻⁷ = 0.000693 s, or 0.693 ms. The output spends 0.7623 ms high against 0.693 ms low every cycle — noticeably closer to even than a large-R1 design would give, but, in this basic three-terminal circuit, never quite there.
Questions
Why is the duty cycle always above 50% in a basic 555 astable?
Because the capacitor charges through R1 and R2 together but discharges through R2 alone, so the high phase (set by R1+R2) is always longer than the low phase (set by R2 alone). The formula (R1+R2)/(R1+2R2) can only approach 50% as R1 shrinks toward zero, never reach or drop below it — an exact 50% needs the diode-assisted variant, which routes charging around R1 with a diode in parallel with R2.
Can R1 be set to zero to flatten the duty cycle?
No. Datasheets specify a minimum R1, commonly a few hundred ohms, because at R1 = 0 the discharge transistor would briefly connect the supply straight to ground every cycle, driving a current spike through the discharge pin large enough to damage the chip — a real hardware limit the formula alone doesn't show.
Where do the 1.44 and 0.693 constants come from?
Both trace back to ln2 ≈ 0.6931, the RC time-constant multiplier for crossing from one-third to two-thirds of the supply voltage, which is exactly the span the 555's two internal comparators watch. The high- and low-time formulas use 0.693 directly, while the frequency formula uses 1.44, a rounded 1/ln2 (actually 1.4427), which is why 1/f and t_high + t_low disagree by under a quarter of one percent.
What frequency range is realistic for a 555 astable?
From well under 1 Hz, using a large electrolytic capacitor with megohm resistors for a slow LED flasher, up to several hundred kilohertz with small ceramic capacitors and resistors in the hundreds of ohms. Past roughly 1 MHz, comparator propagation delay inside the chip starts to matter more than the RC math, and the real frequency falls short of the formula's prediction.
How accurate is the calculated frequency on a real breadboard?
Only as accurate as the parts. Standard resistors run ±5% and many timing capacitors, especially electrolytics, run ±10-20%, so a calculated 685.7 Hz can measure anywhere from roughly 550 Hz to 800 Hz on the bench. For a repeatable frequency, use a tighter capacitor — film or C0G ceramic — and a trimmer on R1 or R2.
Does the supply voltage change the oscillation frequency?
Barely, and only as a second-order effect. Both switching thresholds scale with Vcc (one-third and two-thirds of it), so the fraction the capacitor charges through stays the same and the ideal RC formula is voltage-independent. Real chips drift a percent or two with supply from comparator offset and propagation delay, which is why datasheets plot frequency stability against voltage rather than quoting one number.